1. Field of the Disclosure
The present disclosure relates to a non-volatile memory, and more particularly, to a phase-change random access memory (PRAM) having a structure capable of reducing a reset current and a method for fabricating the same.
2. Description of the Related Art
The PRAM is an element memorizing binary information using characteristics so that a phase-change material such as GeSbTe is changed in its phase into crystalline and amorphous by local heat generation due to an electrical pulse. In the PRAM, a memory cell memorizing the binary information includes a phase-change layer, a resistor, and a switch transistor. The transistor is manufactured on a silicon wafer and the resistor and the phase-change layer are formed on the transistor. The phase-change layer is a so-called GST(GeSbTe)-based material. The phase-change material is a material used for a magnetic recorder that uses media such as a digital video disk (DVD) and a compact disk (CD)-rewritable (RW) and is called chalcogenide. The resistor is intended to heat the phase-change layer. As the phase-change layer is heated, the phase-change layer is changed in its phase into crystalline and amorphous so that the resistance is varied and a voltage is varied due to a current flowing on a resistor, whereby the binary information can be stored and read.
A dynamic random access memory (DRAM), a static random access memory (SRAM), which is a volatile memory, or a flash memory, which is a non-volatile memory store the binary information in form of a “charge” (charge-base memory). On the contrary, the PRAM stores the binary information in form of a “resistance” (resistance-base memory). Accordingly, the PRAM can be differentiated from other memory elements.
For the thin film material used for the PRAM, an alloy of GeSbTe series material is primarily used. This material has a characteristic so that a negative differential resistance property appears when a voltage between 0.6-0.9 volt (V) is applied so that its resistivity is drastically reduced.
Since the above-described PRAM has a large on/off ratio which is one of references discriminating the functionality of a memory device storing the binary information, compared with other memory elements, not only the binary information can be easily discriminated in a circuit but also a circuit maintaining a high voltage is not required. Since the ratio has a scale of more than forty times other memory elements when represented in terms of resistivity, a wide dynamic range can be secured. Therefore, the PRAM has an advantage in its scalability even if small-sizing and integration trends for semiconductor integrated circuit technology are sought. The scalability is advantageous in the commercialization of the PRAM in the future and its distinctive character is apparent when compared with the flash memory. Since a high voltage greater than a power source voltage is required for writing and deleting operations in the flash memory, the circuit design is complicated. On the contrary, since all electrical operations can be performed within an applied power source voltage in the PRAM, power consumption is small.
For commercialization of the PRAM, a variety of research approaches for reducing the reset current of the PRAM are being investigated. For example, the reset current of the PRAM can be reduced by reducing an area size of a bottom electrode contact (BEC) to increase current density. However, there are limitations in the structure of the PRAM by reducing the area of the contact portion. Therefore, the development of other ways to reduce the reset current of the PRAM is required.